The present invention relates to timing analysis in integrated circuit design, and more specifically, to variation-aware timing analysis using waveform construction.
In the design of integrated circuits (ICs) or chips, static timing analysis (STA) is used to determine whether the timing specifications of the chip are satisfied prior to manufacturing. Results of STA drive automated or manual optimization of the chip design in an iterative fashion until all timing specifications are met. STA typically includes performing delay calculation, which involves modeling and calculating path delays for the gates and interconnects of the design, and propagation of arrival times, required arrival times, slews, and slacks for the paths in the design. Specifically, paths in the chip (e.g., from a chip input to a chip output) are analyzed to determine the speed of propagation through the paths and distinguish relatively fast and slow paths. This analysis may be used in the physical synthesis process following which a physical implementation of the chip is generated.